28 July 2011

App Note 13 part 2

The applications section of App Note 13 includes a dozen more of his favorite circuits. There are three voltage-to-frequency converters. The first one (Figure 16) goes to 10 MHz and is based on a feedback charge pump (some similarities to Figure 8 in App Note 7). I really like the trick of replacing the input stage of the LT318A with discrete 2N4393 FETs connected to the op amp's balance terminals. Clever. The second V-to-F circuit (Figure 19) is a quartz-stabilized design that goes to 30 MHz, using a sampled-data DAC in the feedback path. Why doesn't this schematic include the oscillator circuit?

The third V-to-F is shown in Figure 21, with a sine-wave output using an AD639 as a triangle-to-sinusoid converter. I'm sad to see the (now-discontinued) AD639 used this way. The AD639 was a Barrie Gilbert's brilliant Universal Trigonometric Function Converter, and using it as a triangle-to-sinusoid converter is like using a Lamborghini to go get your groceries. It was capable of producing sine over a plus-and-minus 500 degree range, along with cos, tan, sec, csc, cot, arcsin, and other functions, using some really interesting bipolar-transistor tricks. The data sheet and Gilbert's JSSC paper are a fun read. It really was a brilliant chip; too bad nobody really figured out what to do with it.

(B. Gilbert, "A monolithic microsystem for analog synthesis of trigonometric functions and their inverses," IEEE Journal of Solid-State Circuits, vol. 17, no. 6, pp. 1179–1191, Dec. 1982.)

There are also three sample-and-hold circuits, continuing on a theme that he started in National Semiconductor App Note 294, "Special Sample and Hold Techniques." Figure 23 shows a high-speed ramp-and-hold circuit that uses a single-slope-integrator technique to match the input voltage. He uses a 2N5486 JFET to buffer the hold capacitor from the output (in this circuit and the next one). Figure 26 uses a similar topology to implement a track-and-hold circuit that oscillates around the input voltage. Oscillations on purpose? Scary.

Figure 29 revisits a sample-and-hold circuit for repetitive signals from AN-294, although it is improved from a 100-ns sampling window to a 10-ns window. This circuit samples a single voltage at an adjustable delay time after a zero crossing. Just think, with a bank of 32 of these circuits, you could build the front end of an analog sampling oscilloscope.

The next two circuits are analog-to-digital converters. Figure 31 is a two-speed SAR converter (a topology that he will revisit in App Note 17). Figure 33 is a single-slope-integrating converter. Several tricks are used to improve performance, such as the Schottky diode on the latch pin and the temperature-compensating resistor in the current source. Also note Q4, the 2N2222 being used in the reverse-active region to improve the capacitor reset voltage.

Figure 36 shows a high-frequency (2.5 MHz!) precision rectifier that uses a four-diode gate with level-shifted drive like Figure 5 of App Note 10. Figure 38 is a fiber-optic receiver, using a discrete-transistor amplifier for the high-frequency gain stage (Q1 through Q6), and a cute min-max detector (Q6 and Q7) that samples the peaks and valleys of the input signal and calculates the midpoint for the comparator threshold and the level-out monitor.

Figure 40 shows a 12-ns circuit breaker (I like the output stage of Q1, Q2, and the diode that is virtually the same topology as a discrete TTL gate). Figure 42 is a high-speed trigger circuit, using a discrete-transistor FET input buffer and showcasing the high speed of the LT1016 (50 MHz!).

Whew! I'll discuss the appendices tomorrow.


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