Successive approximation is an important analog-to-digital conversion technique, and there are several clever circuits here, but all of the designs use the AM2504 successive approximation register chip, which is no longer available. Certainly, there are plenty of available monolithic ADC chips that internally use the SAR technique, but there are very few stand-alone register chips anymore, so these discrete-design techniques are dated. (The AM2504 family is obsolete, but ON Semiconductor still makes the MC14549 family; however, I think that's it.) For some reason, this app note feels even more obsolete than App Note 1 and the discontinued LT1005.
Figure 1 shows a basic ADC topology using the AM2504 SAR and an AM6012 DAC (good luck finding one of those, too). The conversion time is quoted at 12 microseconds. Note that the only Linear Technology parts here are the LT1021 reference and the LT1011 comparator. (Also note that the AM2504 in Figure 1 is labeled "SAR Register". Is that like "PIN Number" and "ATM Machine"? Sorry, Jim.)
Figure 3 shows a two-speed scheme (similar to App Note 13 Figure 31) that speeds up the conversion clock on the lower bits (when you don't need as much time for settling because the output of the DAC isn't moving as much), achieving 7.5 microseconds. Page AN17-3 shows how to calculate the required comparator gain, and Figure 5 shows how to use a Schottky-diode-bounded LT318A pre-amplifier to meet the gain spec with the much faster, but lower gain, LT1016 comparator (down to 3.5 microseconds). Figure 7 shows a faster discrete pre-amp, using a cascaded differential pair from a CA3127 transistor array (the little base-current compensation circuit is nice).
The best circuit is the fastest: Figure 9, the highest-speed SAR ADC in the app note. Several techniques for speed are used, including the fast preamp and LT1016. (Note that the voltage reference and comparator are still the only LTC parts, but at least there are three LT1016s.) A feedback loop determines the clock speed (fast for large voltage errors, and slow for small voltage errors, allowing extra time for fine settling) and an active clamp (the 74121 and FET) assists the DAC in quick settling. "The circuit achieves a full 12-bit conversion in 1.8us, about the practical limit with off-the-shelf components" (even if the major components (DAC and SAR) aren't carried on anyone's shelf anymore).
The box section on page AN17-8 gives a descriptive analogy for the SAR technique, and talks about some of additional DAC considerations, such as output capacitance, (meaningful) settling time, and monotonicity. The best quote is (page AN17-8) "The successive approximation technique is probably as old as the first crude weighing scale ever constructed."