App Note 18 part 2

The box section on page AN18-12, entitled "The oscillation problem (frequency compensation without tears)" is a bit of a muddle. He seems resolutely determined to avoid the phrase "phase margin". Too bad. Some of the explanation seems tortured in order to avoid saying it. (I feel bad about the following write up, because I really don't like this part of the app note, and Jim can't defend himself. I should have just skipped it.)

Rather than his distinction between "local oscillations" and "loop oscillations", I prefer to distinguish between the "intentional feedback loop" and the "unintentional feedback loops". The first step in the construction of any feedback system is to make sure that the major loop, the intentional feedback loop, is stable. If the major loop doesn't have enough phase margin, then the system will be unstable, regardless of how well it's constructed. (If there are minor loops, they need to be stable, too, of course.) The second step is to make sure than the construction doesn't introduce additional negative phase shift to the major loop, or introduce any unintentional feedback loops through parasitics.

In his parlance, "local oscillations" are caused by a subcircuit, usually the boost stage. Most of these are caused by unintentional feedback loops, as he says, "transistor parasitics, layout and circuit configuration," although a poorly designed intentional feedback loop (a minor loop) within the boost stage could certainly be unstable. I think the important troubleshooting step is to compare what you built with what you meant to build (hence my preference for the distinction between intentional and unintentional loops). Nonetheless, the advice is still good. For example, "avoid high f_t transistors unless they are needed" (that is, minimize the high-frequency gain for all your unintentional loops).

(A side note here: He mentions the use of damper networks, but doesn't mention the drawbacks. In Figure 5a the additional gain of the inverters is removed at high frequency by the 100-ohm and 200-picofarad lag. I'd like to see a careful measurement of how badly that compensation network degrades the settling time.)

His next paragraph is a bit tortured: "Loop oscillations are caused when the added gain stage supplies enough delay to force substantial phase shift. This causes the control amplifier to run too far out of phase with the gain stage." This "too far out of phase" statement is confused. The real issue is the phase margin of the loop. If the phase margin of the combined loop (the control amplifier and the boost stage) is too low, then you've got trouble. It's not an issue of being "in phase".

The advice in the next paragraph is slightly off-base. "If the booster stage has higher gain bandwidth than the control amplifier, its phase delay is easily accommodated in the loop." This isn't exactly right, and counterexamples could be constructed (such as when the gain of the booster stage is larger than unity). Again, the real issue is the phase margin of the combined loop. It is usually true that if the gain-bandwidth of the booster is large, then its phase shift at the unity-gain frequency of the loop will be small, and the phase margin will be sufficient. But there's no guarantee. If you want a guarantee, then you need to determine the combined loop transmission and determine the phase margin.

Repeat after me: "Find the phase margin."

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Related:

• App Note 18 part 1